The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to physical interface macros (PHYs) supporting heterogeneous electrical properties.
In the current world, a data center comprises layers of computers, switches, controllers, and devices. A data center is a department that houses the computer systems and related equipment, such as network switches, routers, and storage. FIG. 1 illustrates a typical data center in the current art. Computers 102-104 connect to a layer of switches, which includes Internet protocol (IP) switch 112, Fibre Channel (FC) switch 114, message passing interface (MPI) switch 116, and switch 118. Switches 112-118 allow computers 102-104 to talk over one or more networks, communicate with storage, and perform total systems management, which is the management of all the computers and devices in the data center.
In the depicted example, IP switch 112 connects computers 102-104 to a wide area network (WAN) and/or local area network (LAN). FC switch 114 connects computers 102-104 to storage controller 122 and storage controller 124, which allow computers 102-104 to read to or write from just a bunch of disks (JBOD) 132 and JBOD 134, respectively. A JBOD is a group of hard disks in a computer or storage enclosure that are not set up as any type of redundant array of independent disk (RAID) configuration. They are just a bunch of disks. The configuration of the disks is handled by storage controllers 122, 124. MPI switch 116 and/or switch 118 allow computers 102-104 to perform total systems management.
FIG. 2 is a block diagram illustrating a typical multiple processor data processing system. In the depicted example, data processing system 200 may be a computer system, such as computers 102-104 in FIG. 1. Data processing system 200 has a plurality of processors 202, 204 connected via a symmetric multiprocessing (SMP) bus 220. Memory controller (MC) 232 and input/output channel controller (IOCC) 234 also connect to SMP bus 220. In the example shown in FIG. 2, IOCC 234 connects to a plurality of expansion slots, such as peripheral component interconnect express (PCI Express or PCIe) slots 236. One or more I/O adapter (not shown) may connect to PCI Express slots 236.
Traditionally, a processor, such as processor 202, would comprise a single core that runs a single thread. Improvements to the core design drove technology to increase effectiveness of the processor. With all this progress, the amount of improvement that can be made to the single core design is approaching a plateau. The next step to improving processor performance was to introduce multiple core designs. Also, a next step was to introduce multi-threaded processor design where each core can execute two or more threads simultaneously. What has resulted is a processor that is capable of an enormous amount of computation per piece of silicon. A processor that was a single core running at 16 MHz has matured into a piece of silicon with eight cores each running at up to 4 GHz and executing multiple threads. All the infrastructure around the processors is not keeping up.